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VHDL, explained for people who think in C++

You already know how to make a CPU run instructions one after another. VHDL is a different universe: you don't write a program, you describe hardware — and hardware is massively parallel and marches to a clock. This page teaches the mental model with live, pokeable visualizations, starting from a single logic gate and building up.

15 worked examples simple → complex interactive waveforms animated diagrams a C/C++ analogy for every concept

The one idea that changes everything: hardware runs in parallel

In a CPU, statements run in order, one per tick of a program counter. In an FPGA, every concurrent statement becomes its own physical circuit that is live every nanosecond, simultaneously. There is no program counter. Press play and watch the same three lines behave completely differently on a CPU vs. in hardware.

the three statements 
a   <= b xor c;   -- one circuit
d   <= a and e;   -- another circuit — runs at the SAME time
sum <= x + y;     -- and a third. all three are always on.

How to read this page

dotted underlinedHover or tap any term like this for a definition and a firmware analogy.
▶ Step / PlayDrive the clock yourself, or let an animation run. Anything clocked only changes on a rising edge.
●●·· dotsDifficulty, 1–5. We start at 1 and ramp up. ⭐ marks the two pivotal examples.
💡 / ⚠️A firmware analogy box and a gotcha box accompany most examples.

Glossary

Every dotted-underlined term on this page lives here too. Filter to find one fast — each entry pairs a definition with a firmware analogy.

This page

A visual companion to your written VHDL guide. Open guide.md alongside it for the deep, Zynq/Vivado-specific material.

Where to go next

  • Nandland — gentle FPGA/VHDL tutorials
  • VHDLwhiz — practical VHDL deep-dives
  • HDLBits — practice problems (Verilog, but the thinking transfers)
  • GHDL — free simulator to run these snippets for real

The golden rules

  • Hardware is parallel; a VHDL file is a schematic in text.
  • State only changes on a clock edge.
  • Always default-assign outputs (no latches).
  • Use numeric_std; cast on purpose.

Built to be opened straight from disk — no server required. Syntax highlighting via Prism (CDN); everything else is vanilla JS + SVG.